(1) Field of the Invention
This invention relates to processes used to fabricate semiconductor devices, and more specifically a process used to integrate logic devices, and memory devices, on a single semiconductor chip.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
The efforts displayed by the semiconductor industry, in attempting to incorporate both logic and memory requirements on a single semiconductor chip have been increasing. One example of this type of invention has been offered by Lee et al, in U.S. Pat. No. 5,792,684. This prior art addresses the incorporation of metal oxide semiconductor field effect transistor, (MOSFET), memory devices, using a self-aligned contact, (SAC), structure for improving the density of memory cell arrays, and MOSFET logic devices, using a Self ALIgned siliCIDE, (Salicide), for improved device performance. However this present invention will offer unique processing sequences, not shown by Lee et al, such as process sequences that will allow the dimension of the MOS memory device to be further decreased, while still allowing the performance of the MOS logic devices to be increased. For example specific rapid thermal anneal procedures, used for activation of source/drain regions, of MOS logic devices, are performed at a stage of the fabrication sequence that will allow a lowering of the self-aligned contact, (SAC), contact resistance, (Rc), to be realized. Another example of unique processing sequences, used in the present invention, is the use of different width spacers, on the sides of the gate structures, for each specific function. For example a wider spacer, needed to allow the use of a robust metal silicide process, for enhanced performance for MOS logic device, is achieved without impacting the use of a thinner spacer, used for the MOS memory device, therefore not increasing the size of the memory cell. Additional unique processing sequences used in this present invention result in the desired, device feature, specific for the memory and logic devices, such as different gate insulator layers, different gate structures, and different lightly doped source/drain, (LDD), regions.